The present invention relates to a level shift circuit for outputting a signal with a high-voltage amplitude.
In recent years, as semiconductor devices have been reduced further in size and power consumption, power source voltages have increasingly lowered. On the other hand, circuits which require high-voltage drive signals are still present so that a level shift circuit for outputting a signal with a high-voltage amplitude is in demand. In the level shift circuit, it is normally necessary to adjust the gate-source breakdown voltage of an output-stage transistor to a level higher than the amplitude voltage of an output signal therefrom. A circuit which includes a high-breakdown-voltage transistor and a low-breakdown-voltage transistor in mixed relation is complicated in circuit design and fabrication process. Moreover, since the high-breakdown-voltage transistor is large in size, the area occupied by the semiconductor device is increased disadvantageously. In view of the foregoing, a method has been examined which allows a level shift circuit for outputting a signal with a high-voltage amplitude to be implemented without using a transistor with a high gate-source breakdown voltage.
For example, Japanese Laid-Open Patent Publication No. 2001-223575 discloses the following level shift circuit. FIG. 7 shows a circuit structure of a level shift circuit according to a conventional embodiment. As shown in FIG. 7, the conventional level shift circuit comprises: an inverter 121 connected between a low-voltage power source terminal TVDD and a ground terminal TVSS and driven by an input signal. The conventional level shift circuit also comprises: a latch circuit 123 connected between the high-voltage power source terminal THVDD and a low-voltage logic terminal THVSS and having an input connected to the output of the inverter 121 via a capacitor 120; and an inverter 125 connected to the output of the latch circuit 123. Each of the outputs of the inverters 121 and 125 is connected to an output circuit 122 connected between the high-voltage power source terminal THVDD and the ground terminal TVSS.
The output circuit 122 is composed of a PMOS output transistor MO102 and an NMOS output transistor MO101 which are connected in series to each other such that the PMOS output transistor MO102 is connected to the high-voltage power source terminal THVDD and NMOS output transistor MO101 is connected to the ground terminal TVSS. The connecting point between the PMOS output transistor MO102 and the NMOS output transistor MO101 is connected to the output terminal TOUT. The gate of the PMOS output transistor MO102 is connected to the output of the inverter 125. The gate of the NMOS output transistor MO101 is connected to the output of the inverter 121.
The potential at the ground terminal TVSS is a ground potential VSS. The potential at the low-voltage power source terminal TVDD is VDD. The potential at the high-voltage power source terminal THVDD is HVDD. The potential at the low-voltage logic terminal THVSS is HVSS. The voltage between the low-voltage, power source terminal TVDD and the ground terminal TVSS and the voltage between the high-voltage power source terminal THVDD and the low-voltage logic terminal THVSS are not more than the gate-source breakdown voltage of each of the transistors composing the circuit. The voltage between the high-voltage power source terminal THVDD and the ground terminal TVSS is not less than the gate-source breakdown voltage of each of the transistors.
When a logic signal at the VDD level is inputted as an input signal from the input terminal TIN and the input signal shifts to the low level, the NMOS output transistor MO101 is turned ON. In addition, a drive signal at the high level is inputted to the latch circuit 123 via the capacitor 120. The PMOS output transistor MO102 is turned OFF by a drive signal outputted from the inverter 125 based on the inputted drive signal. As a result, the potential at the output terminal Tour becomes VSS.
On the other hand, when the input signal is at the high level, the NMOS output transistor MO101 is turned OFF. In addition, a drive signal at the low level is inputted to the latch circuit 123 via the capacitor 120. The PMOS output transistor MO102 is turned ON by a drive signal outputted from the inverter 125 based on the inputted drive signal and the potential at the output terminal TOUT becomes HVDD.
In this case, a drive signal is supplied from the inverter 121 to the output circuit 122 via the latch circuit 123 to the output circuit 122 through current transmission by the capacitor 120. Accordingly, no dc path is present so that a signal with a low-voltage amplitude between the high-voltage power source terminal THVDD and the low-voltage logic terminal THVSS is applied between the gate and source of each of the NMOS output transistor MO101 and the PMOS output transistor MO102. Therefore, it is necessary for the source-drain breakdown voltages of the NMOS output transistor MO101 and the PMOS output transistor MO102 to be set high but, it is sufficient for the gate-source breakdown voltages thereof to be the same as those of the other transistors.
However, the conventional level shift circuit mentioned above has the problem that it requires a high-breakdown-voltage capacitor. The high-breakdown-voltage capacitor occupies an area about 100 times as large as the area occupied by a typical transistor. Therefore, the conventional level shift circuit need not use a transistor with a high gate-source breakdown voltage, but the effect of reducing the area occupied by the semiconductor device can hardly be expected therefrom.